SAK-TC212L-8F133F AC

SAK-TC212L-8F133F AC

General Description:

The TC22x / TC21x product family has the following features: • High Performance Microcontroller with one CPU core • Power Efficient scalar TriCore CPU (TC1.6E), having the following features: – Binary code compatibility with TC1.6P – 133 MHz operation at full temperature range – 88 Kbyte Data Scratch-Pad RAM (DSPR) – 8 Kbyte Instruction Scratch-Pad RAM (PSPR) – 8 Kbyte Instruction Cache (ICACHE) – 4 line read buffer (DRB) • Lockstepped shadow core for TC1.6E • Multiple on-chip memories – All embedded NVM and SRAM are ECC protected – 1 Mbyte Program Flash Memory (PFLASH) – 96 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – BootROM (BROM) • 16-Channel DMA Controller with safe data transfer • Sophisticated interrupt system (ECC protected) • High performance on-chip bus structure – 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (SFI Bridge) • Safety Management Unit (SMU) handling safety monitor alarms • Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU) • Hardware I/O Monitor (IOM) for checking of digital I/O • Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud – Four Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s – One MultiCAN+ Module with 3 CAN nodes each and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer – 4 Single Edge Nibble Transmission (SENT) channels for connection to sensors – One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – One Capture / Compare 6 module (Two kernels CCU60 and CCU61) – One General Purpose 12 Timer Unit (GPT120) • Versatile Successive Approximation ADC (VADC) – Cluster of 2 independent ADC kernels – Input voltage range from 0 V to 5.5V (ADC supply) • Digital programmable I/O ports • On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses) • Four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface

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